1. Field of the Invention
The invention relates to the formation of back end wiring networks for integrated circuits, and particularly to wiring formed by electroplating processes.
2. Related Technology
Semiconductor devices such as integrated circuits (ICs) may include millions of devices, such as metal oxide semiconductor field effect transistors (MOSFETs) and complementary MOSFET (CMOS) circuits. These devices are connected to form circuits through complex back end wiring networks. The typical wiring network is comprised of multiple levels of metal wiring that are inlaid in an insulating material. The individual wires are typically formed by damascene processing. In damascene processing, trenches that define the paths of each wire are formed in a layer of an insulating material such as silicon oxide or a low-k organic insulator. A layer of metal is formed to fill the trenches and cover the surface of the insulator, and then the overburden portion of the metal is polished away, leaving in place only that metal that fills the trenches. Another layer of insulating material is then formed over the metal filled trenches, and another level of wiring is formed in the new layer of insulating material. Vertical conductive structures known as plugs or studs are also formed to connect wiring of different levels and to connect the wiring to contact points of circuit devices. Plugs may be formed in intermediate steps between formation of wiring, or may be formed concurrently with the formation of wiring by dual damascene processing.
Despite the ability of conventional processes to fabricate millions of devices on an IC, there is still a need to decrease the size of IC device features so as to improve the performance of the individual devices, as well as to increase the number of devices on a single IC. The need to decrease device size and increase device speed has led to the adoption of high conductivity metals such as copper for the back end wiring networks of integrated circuits. Electroplating and electroless plating processes have been adopted as the preferred methods of depositing bulk copper in wiring trenches during damascene processing. However, copper does not plate well on conventional insulating materials such as silicon oxide, nor on most of the conductive barrier materials that must be used in copper wiring trenches to prevent diffusion of copper ions into the surrounding insulating material. Therefore, in conventional copper processing, the deposition of bulk copper by a plating processes is preceded by the formation of a thin copper seed layer over the substrate through a process such as physical vapor deposition (PVD). The seed layer is then used as a base layer during subsequent plating.
A typical copper plating process for forming an inlaid (damascene) conductive element is shown in FIGS. 1a-1c. FIG. 1a shows a substrate comprising an upper layer of an interlevel dielectric 10 such as silicon oxide. The silicon oxide 10 has formed therein a wiring trench (or a via) 12 that is to be filled with copper. The surface of the interlevel dielectric 10 is covered with a layer of a barrier material 14 such as TaN that prevents diffusion of copper into the interlevel dielectric 10. FIG. 1b shows the structure of FIG. 1a after formation of a thin copper seed layer 16 by a physical vapor deposition (PVD) process. FIG. 1c shows the structure of FIG. 1b after formation of bulk copper 18 by electroplating or electroless plating. An overburden portion of the bulk copper and other layers on the upper surface of the interlevel dielectric 10 is then removed to leave a copper conductive element inlaid in the trench.
The structure shown in FIG. 1c is idealized, in that it shows that the bulk copper formed in the trench is void-free. However, achieving void-free bulk copper deposition has become more difficult as the result of the continued miniaturization of IC device features. In particular, as the sizes of the IC device features are shrinking, the typical aspect ratios (i.e. ratio of depth to width) of trenches such as those illustrated in FIG. 3c are increasing, which presents problems for conventional seed layer formation.
One significant problem encountered in seed layer formation is illustrated in FIGS. 2a-2b. As shown in FIG. 1b, the seed layer formed by physical vapor deposition is thick on the bottom of the trench and on the top surface of the substrate, but is relatively thin on the sidewalls. Thin sidewalls may result in the formation of voids during a subsequent plating process because the solution in which the substrate is immersed during plating is capable of dissolving copper and may therefore etch through thin portions of the copper seed layer. As shown in FIG. 2a, this may result in the creation of discontinuities 20 in the copper seed layer. Such discontinuities prevent the local formation of copper during the remainder of the plating process. Thus, as shown in FIG. 2b, the discontinuities develop into voids 22 in the bulk copper 18. Such voids increase the resistivity of the copper wiring and may eventually result in circuit failure.
One approach to avoiding the aforementioned problem is to increase the thickness of the seed layer along the sidewalls so that the seed layer will endure the etching that occurs at the beginning of the plating process. However, because the materials deposited by physical vapor deposition processes travel in a generally vertical direction toward the substrate, the amount of seed layer material that is deposited on the vertical sidewalls is relatively small in comparison to the amount of seed layer material deposited on the horizontal surfaces of the substrate and the trench bottom. As a result, the deposited material tends to grow inward more quickly in the areas around the top corners of the trench sidewalls than at the lower portions of the trench sidewalls. This produces a pinching effect, as shown in FIG. 3, that can seal or severely constrict the trench opening if too much material is deposited.
Therefore, continued reduction of device dimensions will require new methods for creating copper wiring that can produce reliable void-free copper wiring elements in trenches and vias that have high aspect ratios.
To address the problems described above, the present invention contemplates a process for depositing void-free, reliable copper or copper-based alloys, or other metal alloys that requires a seed layer to facilitate effective electroplating.
The present invention also provides a method of forming a seed layer in a narrow trench without forming an excessive thickness of seed layer material at upper portions of the trench that could lead to constriction or sealing of the trench opening.
In accordance with embodiments of the invention, a seed layer is formed in a wiring trench through ultra-low energy implantation of the seed layer material in the sidewalls and bottom surface of a trench. The implantation is performed at an angle to the substrate so as to provide sufficient direct implantation of the trench sidewalls. The implantation causes a buildup of seed layer material on the trench sidewalls in a manner that provides essentially continuous and uniform sidewall coverage. Problems of the conventional processing such as void formation and constriction or sealing of the trench by seed layer material are therefore reduced or eliminated.
In accordance with one embodiment of the invention, a wiring for an integrated circuit is formed. Initially, a substrate including an interlevel dielectric layer is provided. The interlevel dielectric layer has a trench for the formation of wiring formed therein. The trench is typically lined with a barrier material, which may be provided as a distinct layer or may comprise a portion of the interlevel dielectric layer at the trench wall surfaces that has been doped with one or more diffusion-preventing material. The substrate is then subjected to a low energy ion implantation process to form a seed layer of a conductive material on the barrier layer. The seed material is preferably copper. The low energy implantation process typically involves implanting seed material at an angle to the surface of the substrate while rotating the substrate continuously or among several stationary positions to achieve approximately even coverage of the trench sidewalls and bottom surface. A plating process is then performed to deposit a bulk conductive material in the trench. The bulk conductive material is preferably copper. Further processing such as removal of an overburden portion of the conductor, formation of a passivation layer, and formation of additional wiring may then be performed.